Semiconductor device package with multi-chips and method of the same

ABSTRACT

The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a structure of semiconductor device package,and more particularly to a structure of semiconductor device packagewith multi-chips and method of the same, the structure can reduce thepackage size and improve the yield and reliability.

2. Description of the Prior Art

In recent years, the high-technology electronics manufacturingindustries launch more feature-packed and humanized electronic products.Rapid development of semiconductor technology has led to rapid progressof a reduction in size of semiconductor packages, the adoption ofmulti-pin, the adoption of fine pitch, the minimization of electroniccomponents and the like. The purposes and the advantages of wafer levelpackage includes decreasing the production cost, decreasing the effectcaused by the parasitic capacitance and parasitic inductance by usingthe shorter conductive line path, acquiring better SNR (i.e. signal tonoise ratio).

Because conventional package technologies have to divide a dice on awafer into respective dies and then package the die respectively,therefore, these techniques are time consuming for manufacturingprocess. Since the chip package technique is highly influenced by thedevelopment of integrated circuits, therefore, as the size ofelectronics has become demanding, so does the package technique. For thereasons mentioned above, the trend of package technique is toward ballgrid array (BGA), flip chip ball grid array (FC-BGA), chip scale package(CSP), Wafer level package (WLP) today. “Wafer level package” is to beunderstood as meaning that the entire packaging and all theinterconnections on the wafer as well as other processing steps arecarried out before the singulation (dicing) into chips (dies).Generally, after completion of all assembling processes or packagingprocesses, individual semiconductor packages are separated from a waferhaving a plurality of semiconductor dies. The wafer level package hasextremely small dimensions combined with extremely good electricalproperties.

In the manufacturing method, wafer level chip scale package (WLCSP) isan advanced packaging technology, by which the die are manufactured andtested on the wafer, and then singulated by dicing for assembly in asurface-mount line. Because the wafer level package technique utilizesthe whole wafer as one object, not utilizing a single chip or die,therefore, before performing a scribing process, packaging and testinghas been accomplished; furthermore, WLP is such an advanced technique sothat the process of wire bonding, die mount and under-fill can beomitted. By utilizing WLP technique, the cost and manufacturing time canbe reduced, and the resulting structure of WLP can be equal to the die;therefore, this technique can meet the demands of miniaturization ofelectronic devices. Further, WLCSP has an advantage of being able toprint the redistribution circuit directly on the die by using theperipheral area of the die as the bonding points. It is achieved byredistributing an area array on the surface of the die, which can fullyutilize the entire area of the die. The bonding points are located onthe redistribution circuit by forming flip chip bumps so the bottom sideof the die connects directly to the printed circuit board (PCB) withmicro-spaced bonding points.

Although WLCSP can greatly reduce the signal path distance, it is stillvery difficult to accommodate all the bonding points on the die surfaceas the integration of die and internal components gets higher. The pincount on the die increases as integration gets higher so theredistribution of pins in an area array is difficult to achieve. Even ifthe redistribution of pins is successful, the distance between pins willbe too small to meet the pitch of a printed circuit board (PCB). That isto say, such process and structure of prior art will suffer yield andreliability issues owing to the huge size of package. The furtherdisadvantage of former method are higher costs and time-consuming formanufacture.

WLP technique is an advanced packaging technology, by which the die aremanufactured and tested on the wafer, and then the wafer is singulatedby dicing for assembly in a surface-mount line. Because the wafer levelpackage technique utilizes the whole wafer as one object, not utilizinga single chip or die, therefore, before performing a scribing process,packaging and testing has been accomplished; furthermore, WLP is such anadvanced technique so that the process of wire bonding, die mount andunder-fill can be omitted. By utilizing WLP technique, the cost andmanufacturing time can be reduced, and the resulting structure of WLPcan be equal to the die; therefore, this technique can meet the demandsof miniaturization of electronic devices.

Though the advantages of WLP technique mentioned above, some issuesstill exist influencing the acceptance of WLP technique. For instance,the coefficient of thermal expansion (CTE) difference (mismatching)between the materials of a structure of WLP and the mother board (PCB)becomes another critical factor to mechanical instability of thestructure. A package scheme disclosed by U.S. Pat. No. 6,271,469 suffersthe CTE mismatching issue. It is because the prior art uses silicon dieencapsulated by molding compound. As known, the CTE of silicon materialis 2.3, but the CTE of molding compound is around 20-80. The arrangementcauses chip location be shifted during process due to the curingtemperature of compound and dielectric layers materials are higher andthe inter-connecting pads will be shifted that will causes yield andperformance problem. It is difficult to return the original locationduring temperature cycling (it caused by the epoxy resin property if thecuring Temp near/over the Tg). It means that the prior structure packagecan not be processed by large size, and it causes higher manufacturingcost.

Further, some technical involves the usage of die that directly formedon the upper surface of the substrate. As known, the pads of thesemiconductor die will be redistributed through redistribution processesinvolving a redistribution layer (RDL) into a plurality of metal pads inan area array type. The build up layer will increase the size of thepackage. Therefore, the thickness of the package is increased. This mayconflict with the demand of reducing the size of a chip.

Moreover, the prior art suffers complicated process to form the “Panel”type package. It needs the mold tool for encapsulation and the injectionof mold material. It is unlikely to control the surface of die andcompound at same level due to warp after heat curing the compound, theCMP process may be needed to polish the uneven surface. The cost istherefore increased.

In view of the aforementioned, the present invention provides a newstructure with multi-chips and method for a panel scale package (PSP) toovercome the above drawback.

SUMMARY OF THE INVENTION

The present invention will descript some preferred embodiments. However,it is appreciated that the present invention can extensively perform inother embodiments except for these detailed descriptions. The scope ofthe present invention is not limited to these embodiments and should beaccorded the following claims.

One objective of the present invention is to provide a structure ofsemiconductor device package and method of the same, which can provide anew structure of super thin package.

Another objective of the present invention is to provide a structure ofsemiconductor device package and method of the same, which can allow abetter reliability due to the substrate and the PCB have the samecoefficient of thermal expansion (CTE).

Still another objective of the present invention is to provide astructure of semiconductor device package and method of the same, whichcan provide a simple process for forming a semiconductor device package.

Yet another objective of the present invention is to provide a structureof semiconductor device package and method of the same, which can lowercost and higher yield rate.

Another objective of the present invention is to provide a structure ofsemiconductor device package and method of the same, which can provide agood solution for low pin count device.

The present invention provides a structure of semiconductor devicepackage comprising a substrate with at least a die receiving throughhole, connecting through holes structure and first contact pads on anupper surface and second contact pads on a lower surface of thesubstrate; at least a first die having first bonding pads disposedwithin the die receiving through hole; a first adhesion material formedunder the first die; a second adhesion material filled in the gapbetween the first die and sidewalls of the die receiving though hole ofthe substrate; a first bonding wire formed to couple to the firstbonding pads and the first contact pads; at least a second die havingsecond bonding pads disposed on the first die; a second bonding wireformed to couple to the second bonding pads and the first contact pads;a die attached tape formed under the second die; and a dielectric layerformed on the first and second bonding wire, the first and second dieand the substrate.

The present invention provides a method for forming a semiconductordevice package comprising providing at least a substrate with a diereceiving through hole, connecting through holes structure and firstcontact pads on an upper surface and second contact pads on a lowersurface of the substrate; redistributing desired at least first diehaving first bonding pads on a die redistribution tool with desiredpitch by a pick and place fine alignment system; bonding the substrateto the die redistribution tool; filling a first adhesion material on theback side of the die; filling a second adhesion material into the spacebetween the die edge and the die receiving through hole of thesubstrate, it maybe fill the first and second adhesion materials at thesame time by using the same materials; separating the “panel” (panelform means substrate with die and adhesion together) from the dieredistribution tool; forming a first bonding wire to connect the firstbonding pads and the first contact pads; placing at least a second diehaving second bonding pads on the first die; forming a second bondingwire to connect the second bonding pads and the first contact pads;forming second bonding wire to connect the bonding pads to the secondcontact pads; printing or molding or dispensing a dielectric layer onthe active surface of the first die and upper surface of the substrate;and mounting the package structure (in panel form) on a tape to saw intoindividual die for singulation.

The present invention provides a method for forming a semiconductordevice package comprising providing a substrate with at least a diereceiving through hole, connecting through hole structure and firstcontact pads on an upper surface and second contact pads on a lowersurface of the substrate; bonding the substrate to a die redistributiontool; redistributing desired at least first die having first bondingpads on the die redistribution tool with desired pitch into the diereceiving through hole of the substrate by a pick and place finealignment system; forming a first bonding wire to connect the firstbonding pads and the first contact pads; placing at least a second die(with adhesion tape on the back side of die) having second bonding padson the first die; forming a second bonding wire to couple the secondbonding pads and the first contact pads; forming a dielectric layer onthe active surface of the first and second die and upper surface of thesubstrate and the gap between the first die and sidewall of the diereceiving through hole; separating the “panel” (panel form meanssubstrate with the die and the adhesion material—in here is dielectriclayer) from the die redistribution tool; and mounting the packagestructure (in panel form) on a tape to saw into individual die forsingulation.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of thisinvention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,taken in conjunction with the accompanying drawings, wherein:

FIG. 1 illustrates is a cross-section diagram of a structure ofsemiconductor device package according to one embodiment of the presentinvention;

FIG. 2 a illustrates is a cross-section diagram of a structure ofsemiconductor device package according to another embodiment of thepresent invention;

FIG. 2 b illustrates is a cross-section diagram of a structure ofsemiconductor device package according to another embodiment of thepresent invention;

FIG. 3 illustrates is a cross-section diagram of a structure ofsemiconductor device package according to another embodiment of thepresent invention;

FIG. 4 illustrates a bottom view diagram of a structure of semiconductordevice package according to the present invention;

FIG. 5 illustrates a top view diagram of a structure of semiconductordevice package according to one embodiment of the present invention;

FIG. 6 a-6 d illustrate cross-section diagrams of a method of forming asemiconductor device package according to one embodiment of the presentinvention; and

FIG. 7 a-7 g illustrate cross-section diagrams of a method of forming asemiconductor device package according to another embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In the following description, numerous specific details are provided inorder to give a through understanding of embodiments of the invention.Referring now to the following description wherein the description isfor the purpose of illustrating the preferred embodiments of the presentinvention only, and not for the purpose of limiting the same. Oneskilled in the relevant art will recognize, however, that the inventionmay be practiced without one or more of the specific details, or withother methods, components, materials, etc.

Referring to FIG. 1, it is a cross-section diagram of a structure ofsemiconductor device package 100 according to one embodiment of thepresent invention. The package 100 comprises a substrate 102, a firstdie 104, a die receiving through hole 105, a first adhesion material106, a second adhesion material 107, first bonding pads 108, a metal orconductive layer 110, a first bonding wire 112, first contact pads 113,connecting through holes structure 114, second contact pads 115, asecond die 122, second bonding pads 126, a die attached tape 124, asecond bonding wire 128, a dielectric layer 118 and a plurality ofconductive bumps 120.

In FIG. 1, the substrate 102 has a die receiving through hole 105 formedtherein to receive a first die 104. The die receiving through hole 105is formed from the upper surface of the substrate 102 through thesubstrate 102 to the lower surface of the substrate 102. The diereceiving through hole 105 is pre-formed within the substrate 102. Thefirst adhesion material 106 is coated (taped) under the lower surface ofthe first die 104, thereby sealing the first die 104. The secondadhesion material 107 is also refilled within the space between the edgeof first die 104 and the sidewalls of the die receiving through holes105. It maybe uses the same material for both the first adhesionmaterial 106 and the second adhesion material 107.

The substrate 102 further comprises the connecting through holesstructure 114 formed therein. The first contact pads 113 and the secondcontact pads 115 (for organic substrate) are respectively formed on theupper surface and lower surface of the connecting through holesstructure 114 and partial part of the upper surface and lower surface ofthe substrate 102. The conductive material is re-filled into theconnecting through holes structure 114 for electrical connection, it ispre-formed process once making the substrate 102.

Optional, a metal or conductive layer 110 is coated on the sidewall ofthe die receiving through hole 105, that is to say, the metal layer 110is formed between the first die 104 surrounding by the second adhesionmaterial 107 and the substrate 102. It can improve the adhesion strengthbetween die edge and sidewall of the die receiving through hole 105 ofthe substrate 102 by using some particular adhesion materials,especially for the rubber type adhesion materials.

The first die 104 is disposed within the die receiving through holes 105on the substrate 102. As know, first bonding pads 108 are formed withinthe upper surface of the first die 104. A first bonding wire 112 isformed to couple to the first bonding pads 108 and the first contactpads 113.

The present invention further comprises a second die 122 formed on a dieattached tape 124 and then placed on the active surface of the first die104. In other words, the second die 122 is placed on the first die 104to expose the first bonding pads 108 for electrical connection. Thesecond die 122 has a plurality of second bonding pads 126 formed on theupper surface of the second die 122. A second bonding wire 128 is formedto couple to the second bonding pads 126 and the first contact pads 113.Next, a dielectric layer 118 is formed to cover the first bonding wire112, the second bonding wire 128, the upper surface of the first die 104and the second die 122 and the substrate 102.

Then, a plurality of conductive bumps 120 are formed and coupled to thesecond contact pads 115 by printing the solder paste on the surface,followed by performing re-flow process to reflow the solder paste.Accordingly, the first die 104 and the second die 122 can beelectrically connected with the conductive bumps 120 via the throughholes structure 114, the first bonding wire 112 and the second bondingwire 128.

The dielectric layer 118 is employed to prevent the package fromexternal force that may causes damage to the package. The metal layer110 and the second adhesion material 107 act as buffer areas that absorbthe thermal mechanical stress between the first die 104 and substrate102 during temperature cycling due to the second adhesion material 107has elastic property. The aforementioned structure constructs LGA typepackage (peripheral type).

In one embodiment, the material of the substrate 102 includes epoxy typeFR5, FR4 or BT (Bismaleimide triazine epoxy). The material of thesubstrate 102 also can be metal, alloy, glass, silicon, ceramic or printcircuit board (PCB). The alloy further includes alloy 42 (42% Ni-58% Fe)or Kovar (29% Ni-17% Co-54% Fe). Further, the alloy metal is preferablycomposed by alloy 42 that is a nickel iron alloy whose coefficient ofexpansion makes it suitable for joining to silicon chips in miniatureelectronic circuits and consists of nickel 42% and ferrous (iron) 58%.The alloy metal also can be composed by Kovar which consists of nickel29%, cobalt 17% and ferrous (iron) 54%.

Preferably, the material of the substrate 102 is organic substrate likesepoxy type FR5, BT, PCB with defined through holes or Cu metal with preetching circuit. Preferably, the coefficient of thermal expansion (CTE)is the same as the one of the mother board (PCB), and then the presentinvention can provide a better reliability structure due to the CTE ofthe substrate 102 is matching with the CTE of the PCB (or mother board)accordingly. Preferably, the organic substrate with high Glasstransition temperature (Tg) are epoxy type FR5 or BT (Bismaleimidetriazine) type substrate. The Cu metal (CTE around 16) can be used also.The glass, ceramic, silicon can be used as the substrate. The secondadhesion material 107 is formed of silicone rubber elastic materials.

In one embodiment, the material of the first adhesion material 106 andthe second adhesion material 107 include ultraviolet (UV) curing typeand thermal curing type material, epoxy or rubber type material. Thefirst adhesion material 106 also can be included the metal material.Further, the material of the dielectric layer 118 includes liquidcompound, resin, silicone rubber and also can be benzocyclobutene (BCB),Siloxane polymer (SINR) or polyimide (PI).

In one embodiment, the material of the die attached tape 124 includes,but not limiting to, elastic material. The die attached tape 124 hasspace balls inside which acts as buffer area that absorbs the thermalmechanical stress between the first die 104 and the second die 122during temperature cycling and UV curing.

Referring to FIG. 2 a, it is a cross-section diagram of a structure ofsemiconductor device package 200 according to another embodiment of thepresent invention. The substrate 202 comprises the connecting throughholes structure 214 formed on four sides of the substrate 202, that isto say, the connecting through holes structure 214 is respectivelyformed on both lateral sides of the substrate 202 (maybe four endsides). The first contact pads 213 and the second contact pads 215 arerespectively formed on the upper surface and lower surface of theconnecting through holes structure 214 and partial part of the uppersurface and lower surface of the substrate 202. The conductive materialis re-filled into the connecting through holes structure 214 forelectrical connection.

Further, the package structure 200 comprises a second die 222 having aplurality of second bonding pads 226 formed on the upper surface of thesecond die 222. The second die 222 is formed on a die attached tape 224,followed by placing the second die 222 on the active surface of thefirst die 204. In other words, the second die 222 is placed on the firstdie 204 to expose the first bonding pads 208 for electrical connection.A second bonding wire 218 is formed to couple the second bonding pads226 and the first contact pads 213. Then, a plurality of conductivebumps 220 are coupled to the second contact pads 215. Accordingly, thefirst bonding pads 208 formed within the first die 204 and the secondbonding pads 226 formed within the second die 222 can be electricallyconnected with the conductive bumps 220 by the connecting through holesstructure 214, the first bonding wire 212 and the second bonding wire228.

Optionally, a metal or conductive layer 210 is coated on the sidewall ofthe die receiving through hole 205, namely, the metal layer 210 isformed between the first die 204 surrounding by the second adhesionmaterial 207 and the substrate 202.

Further, various elements in the package 200 are similar to the elementsin the package 100, as shown in FIG. 1 and 2, and therefore, thedetailed description is omitted.

In FIG. 2 b, illustrates is a cross-section diagram of a structure ofsemiconductor device package 200 according to the present invention. Thefirst contact pads 213 are formed over the connecting through holesstructure 214. The connecting through holes structure 214 is located inthe scribe line 230. In other words, each package has half through holesstructure 214 after sawed. It can improve the solder join quality duringSMT process and also can reduce the foot print. Similarly, the structureof half through holes structure 214 can be formed on the sidewall of thedie receiving through hole 205 (does not show on the drawing), it canreplace the conductive layer 210. Optionally, the above through holesstructure 214 is also called the connecting trench.

Referring to FIG. 3, it is a cross-section diagram of a structure ofsemiconductor device package 200 according to the present invention. Analternative embodiment can be seen in FIG. 3, a package structure 200can be formed without the conductive bumps 220 on the second terminalpads 215. The other parts are similar to FIG. 1, therefore, the detaileddescription is omitted.

Preferably, the thickness a from the surface of the layer 118 to theupper surface of the substrate 102 is approximately 118-218 μm. Thethickness b from the upper surface of the substrate 102 is approximately100-150 μm. Accordingly, the present invention can offer a super thinstructure having a thickness less than 500 μm, and the package size isapproximately around the die size plus 0.5 mm to 1 mm per side to form achip scale package (CSP) by using the conventional process of printcircuit board.

Referring to FIG. 4, it illustrates a bottom view diagram of a structureof semiconductor device package 100 according to the present invention.The back side of the package 100 includes the substrate 102 (solder masklayer is not showed on the drawing) and the second adhesion layer 107formed therein and surrounded by a plurality of second contact pads 115.The package 100 comprises a metal layer 150 sputtering or electroplatingon back side of the first die 104 to replace the first adhesion material106, it maybe enhance the thermal conductivity, as shown in the externaldotted area. The internal dotted area is an indicated area as the areaof the second die 122. The metal layer 150 can be solder join withprinted circuit board (PCB) by solder paste, it can exhaust the heat(generate by die) through the copper metal of print circuit board.

Referring to FIG. 5, it illustrates a top view diagram of a structure ofsemiconductor device package 100 according to the present invention. Thetop side of package 100 includes the substrate 102, a first die 104formed on the first adhesion material 106. A plurality of first contactpads 113 are formed surrounding around the edge areas of the substrate102. The first bonding wire 112 is formed to couple the first bondingpads 108 and the first contact pads 113. Further, a second die 122 isformed on the first die 104 to expose the first bonding pads 108. Thesecond bonding wire 128 couples to the second bonding pads 126 and thefirst contact pads 113. It is noted that the bonding wire 112 and thesecond bonding wire 128 are invisible after the formation of thedielectric layer 118.

Otherwise, the package 100 can be applied to higher pin counts. Theembodiment is similar to FIG. 5, therefore, the detailed description isomitted. Accordingly, the peripheral type of the present invention canprovide a good solution for low pin count device.

According to the aspect of the present invention, the present inventionfurther provides a method for forming a semiconductor device package 100with multi-chips, such as the first die 104 and the second die 122.Refer to FIG. 6 a-6 d, they illustrate a cross-section diagrams of amethod of forming a semiconductor device package 100. The steps are asfollows and the following steps also can be referred to FIG. 7 a-7 f dueto they are similar.

First, the substrate 102 with the die receiving through holes 105,connecting through holes structure 114 and the first contact pads 113 onan upper surface and the second contact pads 115 on a lower surface ofthe substrate 102 is provided, wherein the die receiving through holes105 and the connecting through holes structure 114 and the first contactpads 113 and the second contact pads 115 are preformed within thesubstrate 102, as shown in FIG. 6 a. The desired first die 104 havingfirst bonding pads 108 are redistributed on a die redistribution tool300 with desired pitch by a pick and place fine alignment system, asshown in FIG. 6 b. The substrate 102 is bonding to the dieredistribution tool 300, that is to say, the active surface of the die104 is sticking on the die redistribution tool 300 printed by patternedglues (not shown). After the second adhesion material 107 filled intothe space between the first die 104 and the first adhesion material 106on back side of the first die 104, the first and second adhesionmaterial 106 and 107 are cured, in this application, it maybe the samematerials for the first adhesion material 106 and the second adhesionmaterial 107. Then, the package structure is separated from the dieredistribution tool 300.

After cleaning the top surface of the first bonding pads 108 and thefirst contact pads 113 (the pattern glues may residue on the surface offirst bonding pads 108 and first contact pads 113), the first bondingwire 112 is formed to connect the first bonding pads 108 to the firstcontact pads 113, as shown in FIG. 6 c. Subsequently, a second die 204is formed on the die attached tape 214 and followed by placing the die204 on the first die 202. The second die 204 does not cover the firstbonding pads 108, so that the first bonding pads 108 are exposed forelectrical connection. The second die 202 has the second bonding pads126 formed thereon. Then, the second bonding wire 128 is coupled thesecond bonding pads 126 and the first contact pads 113.

Next, the dielectric layer 118 is coated (or molding or printing ordispensing) and cured on the active surface of the first die 104, thesecond die 122 and upper surface of the substrate 102 in order toprotect the first bonding wire 112, the first die 104, the secondbonding wire 128, the second die 122 and the substrate 102, as shown inFIG. 6d. The terminal contact pads are formed on the second contact pads115 by printing the solder paste (or ball). Then, the plurality ofconductive bumps 120 are formed by an IR reflow method and coupled tothe second contact pads 115. Subsequently, the package structure ismounting on a tape 302 for die singulation.

Optionally, a metal or conductive layer 110 is formed on the sidewall ofdie receiving through hole 105 of the substrate 102, the metal ispre-formed during the manufacture of the substrate. A metal film (orlayer) can be sputtered or plated on the back side of the first die 104as the first adhesion material 106 for better thermal managementinquiry.

According to another aspect of the present invention, the presentinvention also provides another method for forming a semiconductordevice package 200 with the die receiving through holes 205 and theconnecting through holes structure 214. Refer to FIG. 7 a-7 h theyillustrate cross-section diagrams of a method of forming a semiconductordevice package 200 according to the present invention

The steps of forming the package 200 comprises providing a substrate 202with die receiving through holes 205, connecting through holes structure215 and the first contact pads 213 on an upper surface and a secondcontact pads 215 on a lower surface of the substrate 202. The substrate202 is bonding to a die redistribution tool 300, as shown in FIG. 7 a.In other words, the active surface (for solder join) of the substrate202 is sticking on the die redistribution tool 300 printed by patternedglues (not shown). The desired first die 204 has first bonding pads 208formed on the upper surface of the first die 204, and the first adhesionmaterial 206 (optional—it maybe the adhesion tape) is formed on the backside of the first die 204, as shown in FIG. 7 b. The first die 204 isredistributed on the die redistribution tool 300 with desired pitch by apick and place fine alignment system. Then, the first bonding wire 212is formed to connect the first bonding pads 208 to the first contactpads 213, as shown in FIG. 7 c.

Subsequently, the second die 222 is formed on the die attached tape 224and then formed on the first die 204 to expose the first bonding pads208, as shown in FIG. 7 d. The second die 222 has the second bondingpads 226 formed within the second die 222. Then, the first adhesionmaterial 206 and the die attached tape 224 are cured. The second bondingwire 228 is formed to couple the second bonding pads 226 and the firstcontact pads 213, as shown in FIG. 7 e.

Next, the dielectric layer 218 is formed on the active surface of thefirst die 204, the second die 222 and upper surface of the substrate 202to fully cover the first bonding wire 212 and the second bonding wire228 and fill into the gap between die edge and sidewall of die receivingthrough hole 205 as second adhesion material 207, as shown in FIG. 7 f,and then the dielectric layer 218 is cured. After the package structureseparated from the die redistribution tool 300, the back side of thesubstrate 202 and the first adhesion material 206 are cleaned, as shownin FIG. 7 g.

Alternatively, the terminal contact pads are formed on the secondcontact pads 215 by printing the solder paste (or ball). Optionally, theplurality of conductive bumps 220 are formed and coupled to the secondcontact pads 215. Subsequently, the package structure 200 is mounted ona tape 302 for die singulation.

In one embodiment, a conventional sawing blade 232 is used during thesingulation process. The blade 232 is aligned to the scribe line 230 toseparate the dice into individual die during the singulation process, asshown in FIG. 7 h.

Optionally, a metal or conductive layer 210 is formed on the sidewall ofdie receiving through hole 205 of the substrate 202, it is pre-formed asmentioned above. Another process is used to form the first adhesionmaterial 206 by using the steps including seed metal sputtering,patterning, electro-plating (Cu), PR stripping, metal wet etching etc.to achieve the metal layer 150.

In one embodiment, the step of forming the conductive bumps 120 and 220are performed by an infrared (IR) reflow method.

It is noted that the material and the arrangement of the structure areillustrated to describe but not to limit the present invention. Thematerial and the arrangement of the structure can be modified accordingto the requirements of different conductions.

According to the aspect of the present invention, the present inventionprovides a structure of semiconductor device with the die receivingthrough hole and the connecting through holes structure, that provides astructure of super thin package which the thickness is less than 500 μmand the package size is slight large than the die size. Further, thepresent invention provides a good solution for low pin count device dueto the peripheral type format. The present invention provides a simplemethod for forming a semiconductor device package which can improve thereliability and yield. Moreover, the present invention further providesa new structure that has multi-chips, and therefore can also minimizethe size of chip scale package structure and lower costs due to thelower cost material and the simple process. Therefore, the super thinchip scale package structure and method of the same disclosed by thepresent invention can provide unexpected effect than prior art, andsolve the problems of prior art. The method may apply to wafer or panelindustry and also can be applied and modified to other relatedapplications.

As will be understood by a person skilled in the art, the foregoingpreferred embodiments of the present invention are illustrative of thepresent invention, rather than limiting the present invention. Havingdescribed the invention in connection with a preferred embodiment,modification will suggest itself to those skilled in the art. Thus, theinvention is not to be limited by this embodiment. Rather, the inventionis intended to cover various modifications and similar arrangementsincluded within the spirit and scope of the appended claims, the scopeof which should be accorded the broadest interpretation so as toencompass all such modifications and similar structures.

1. A structure of semiconductor device package, comprising: a substratewith at least a die receiving through hole, connecting through holesstructure and first contact pads on an upper surface and second contactpads on a lower surface of said substrate; at least a first die havingfirst bonding pads disposed within said die receiving through hole; afirst adhesion material formed under said first die; a second adhesionmaterial filled in the gap between said first die and sidewalls of saiddie receiving though hole of said substrate; a first bonding wire formedto couple to said first bonding pads and said first contact pads; atleast a second die having second bonding pads disposed on said firstdie; a second bonding wire formed to couple to said second bonding padsand said first contact pads; a die attached material formed under saidsecond die; and a dielectric layer formed on said first and secondbonding wire, said first and second die and said substrate.
 2. Thestructure in claim 1, further comprising a plurality of conductive bumpscoupled to said second contact pads.
 3. The structure in claim 2,wherein said plurality of conductive bumps can be electrically connectedwith said bonding pads through said through holes structure.
 4. Thestructure in claim 1, further comprising a metal or conductive layerformed on side walls of said die receiving through hole of saidsubstrate.
 5. The structure in claim 1, wherein said connecting throughholes structure is formed to pass through said substrate.
 6. Thestructure in claim 1, wherein said connecting through holes structure isformed lateral side of said substrate.
 7. The structure in claim 1,wherein material of said substrate includes epoxy type FR5, FR4 or BT(Bismaleimide triazine).
 8. The structure in claim 1, wherein materialof said substrate includes metal, alloy, glass, silicon, ceramic orprint circuit board (PCB).
 9. The structure in claim 8, wherein saidalloy includes alloy 42 (42% Ni-58% Fe) or Kovar (29% Ni-17% Co-54% Fe).10. The structure in claim 1, wherein material of said first adhesionmaterial and second adhesion material include UV curing type and thermalcuring type material, epoxy or rubber type material.
 11. The structurein claim 1, wherein material of said die attached material includeselastic material.
 12. The structure in claim 1, wherein said connectingthrough holes structure is filled by a conductive material.
 13. Thestructure in claim 1, wherein material of said dielectric layer includeliquid compound, resin and silicone rubber.
 14. The structure in claim1, wherein material of said dielectric layer include benzocyclobutene(BCB), Siloxane polymer (SINR) or polyimide (PI).
 15. The structure inclaim 1, wherein material of said first adhesion material include ametal sputtering and/or electro-plating on back side of said first die.16. A method for forming a semiconductor device package, comprising:providing a substrate with at least a die receiving through hole,connecting through holes structure and first contact pads on an uppersurface and second contact pads on a lower surface of said substrate;redistributing desired at least first die having first bonding pads on adie redistribution tool with desired pitch by a pick and place finealignment system; bonding said substrate to said die redistributiontool; filling a first adhesion material on the back side of said dice;filling a second adhesion material into the space between said dice edgeand said dice receiving through hole of said substrate; separating saidpackage structure from said die redistribution tool; forming a firstbonding wire to connect said first bonding pads to said first contactpads; placing at least a second die having second bonding pads on saidfirst die; forming a second bonding wire to connect said second bondingpads and said first contact pads; printing a dielectric layer on theactive surface of said first and second die and upper surface of saidsubstrate; and mounting said package structure on a tape to saw intoindividual die for singulation.
 17. The method in claim 16, furthercomprising a step of welding a plurality of soldering bumps on saidterminal pads.
 18. The method in claim 17, wherein said step of formingsaid soldering bumps is performed by an infrared (IR) reflow method. 19.The method in claim 17, wherein said step of forming said conductivebumps on said second contact pads is performed by solder paste.
 20. Themethod in claim 16, further comprising a step of sticking active surfaceof said first die on said die redistribution tool printed by patternedglues.
 21. The method in claim 16, further comprising a step of curingsaid first and second adhesion material.
 22. The method in claim 16,further comprising a die attached tape formed under said second die. 23.The method in claim 22, wherein material of said die attached tapeincludes elastic material.
 24. The method in claim 16, furthercomprising a step of curing said dielectric layer.
 25. The method inclaim 16, further comprising a step of forming a metal or conductivelayer on the sidewall of said die receiving through hole of saidsubstrate.
 26. The method in claim 16, further comprising a step ofcleaning top surface of said package before forming said bonding wire.27. A method for forming a semiconductor device package, comprising:providing a substrate with at least a die receiving through hole,connecting through holes structure and first contact pads on an uppersurface and second contact pads on a lower surface of said substrate;bonding said substrate to a die redistribution tool; redistributingdesired at least first die having first bonding pads on said dieredistribution tool with desired pitch by a pick and place finealignment system; forming a first bonding wire to connect said firstbonding pads to said contact pads; placing at least a second die havingsecond bonding pads disposed on said first die; forming a second bondingwire to connect said second bonding pads and said first contact pads;forming a dielectric layer on the active surface of said first andsecond die and upper surface of said substrate and fill into the gapbetween dice edge and sidewall of said die receiving through hole ofsaid substrate; separating said package structure from said dieredistribution tool; and mounting said package structure on a tape tosaw into individual die for singulation.
 28. The method in claim 27,further comprising a step of welding a plurality of conductive bumps onsaid second contact pads.
 29. The method in claim 28, wherein said stepof forming said conductive bumps is performed by an infrared (IR) reflowmethod.
 30. The method in claim 28, wherein said step of forming saidconductive bumps on said second contact pad is performed by solderpaste.
 31. The method in claim 27, further comprising a step of stickingbackside surface of said first die on said die redistribution toolprinted by patterned glues.
 32. The method in claim 27, furthercomprising a step of curing said dielectric layer.
 33. The method inclaim 27, further comprising a step of forming a first adhesion materialon the back side of said first die.
 34. The method in claim 27, furthercomprising a die attached tape formed on the back side of said seconddie.
 35. The method in claim 34, wherein material of said die attachedtape includes elastic material.
 36. The method in claim 27, furthercomprising a step of forming a metal layer on the sidewall of said diereceiving through holes of said substrate.